Fabrication of integrated circuits (ICs) typically includes numerous steps of deposition, diffusion, etching, implantation, lithography, etc. Inherent variations in each of these processes can result in transistor devices having individual threshold voltages (Vt) that are slightly higher, or lower, than desired and/or result in the effective gate length of the individual transistor devices varying slightly from an ideal value. Consequently, variations in transistor threshold voltages can arise due to such process variations.
In addition, variations in biasing or power supply voltages, and environmental factors can further impact device or IC performance. A device (e.g., transistor) if not an entire IC can either speed up or slow down due variations in biasing or supply voltages applied to individual devices or applied globally across the IC. Variations in temperature around the IC or a particular device can also have a substantial effect on the operation of the device.
Any one or all of these process, voltage and temperature (PVT) variations can have a significant effect on the performance of that device causing a reduction in timing margins and/or switching frequency. In particular, variations in threshold voltage (Vt) across expected process variations and operating temperatures has become a major problem in deep sub-micron designs, where a power supply voltage is, or may become low with respect to higher device size circuits.
A conventional method is known that can compensate for process variation (including Vt variation) in, for example, output drivers. Such a method is shown in “A Slew-Rate Controlled Output Driver Using PLL as Compensation Circuit”, IEEE Journal of Solid States Circuit, Vol. 38, No. 7, July 2003, pp. 1227–1233, by Shin et al. According to such a conventional approaches, a control voltage of a Voltage Controlled Oscillator (VCO) can compensate an output driver slew rate in the event Vt variation alters the output driver performance. More particularly, the above conventional approach can use a control voltage of a VCO in a Phase Locked Loop (PLL) formed on the same die as the IC as an indicator for process variation, including Vt variations. Such a control voltage can then be used to compensate the slew rate of the output driver. Variation of slew rate can be reduced by about 25% percent based on the VCO control voltage.
Although the above conventional approach provides an improvement over previous uncompensated designs, the above conventional approach may not be wholly satisfactory for a number of reasons. First, PLLs can occupy a significant amount of area on the die, and can be difficult to design/fabricate using present process technology. Second, a VCO control voltage may reflect only a general trend of the Vt variation, and hence may not necessarily be a precise indicator of Vt variation across the IC or in a particular device.
Accordingly, there is a need for a new on-chip circuit and method for automatically calculating or measuring the variations in the Vt of metal-oxide-semiconductor (MOS) type transistors in an IC at arbitrary locations.
Further, it is also desirable that the results of the calculated or measured variations in Vt can then be used to compensate Vt-sensitive blocks, where Vt mismatch/variation affects the circuit performance. As but one particular example, it is desirable that the results can be used for body biasing in a triple well process, where speed gain or leakage current reduction can be achieved by biasing the substrate/well.